Various methods of measuring the stress in films deposited on semiconductor wafers are known in the art. Most commonly, the measurement is performed by measuring the shape of the wafer before a process step and then repeating the shape measurement after the process step. The stress of a film deposited (or removed) during the process step is calculated from the change in shape of the wafer and the known elastic modulus of the semiconductor material comprising the bulk of the wafer. The thickness of the wafer and/or film may be known prior to the shape measurement, or may be measured by the same apparatus making the shape measurement. If the stress and film thickness are reasonably uniform across the wafer and if the change in shape of the wafer is not large compared with the thickness of the wafer (all of which conditions are usually satisfied by most semiconductor manufacturing process steps), then Stoney's equation (G. G. Stoney (1909) Proc. Roy. Soc. A82, 172) may be used to calculate the film stress from the change in wafer curvature deduced from the change in wafer shape.
U.S. Pat. Nos. 5,134,303 and 5,248,889 (Blech et al) disclose a technique for scanning laser beams along a diameter of a wafer in order to measure the slope, and hence, curvature of the wafer. It will be understood by those of ordinary skill in the art that either the beam may be scanned across the wafer or the wafer may be moved under the beam in order to perform the measurement. If the stress of the film is uniform, measurement of a single diameter usually suffices. If the stress of the film is non-uniform, measurement of multiple diameters is often needed to build up a more complete picture of the wafer curvature.
U.S. Pat. No. 5,912,738 to Chason et al. describes a technique that uses multiple laser beams to make simultaneous measurements of slope at multiple locations on a wafer, thus speeding up the measurement by reducing, or eliminating, the need for relative scanning of the beam and wafer.
U.S. Pat. No. 6,031,611 to Rostakis et al. describes a technique that is capable of measuring slope (in one direction) simultaneously at many points across the whole surface of a wafer. A second measurement can be made with the wafer rotated by 90° in order to measure the other tilt component if that is also desired.
As an alternative to measuring the tilt of the wafer, it is also possible to measure the displacement of the wafer as a function of position across the wafer. U.S. Pat. No. 4,750,141 to Judell et al. discloses such a technique. The displacement measurement may be done with capacitive sensors (as disclosed in '141) or by optical or other means. U.S. Pat. No. 6,100,977 to Muller and U.S. Pat. No. 6,847,458 to Freischlad et al. disclose techniques that are capable of essentially simultaneously measuring the displacement of both sides of the of wafer using optical interferometers.
Other methods of measuring stress are known in the art. These other methods are generally less convenient for use in a production environment than the change in wafer shape metrology just described because these other techniques are generally slower or require more expensive hardware.
High resolution X-ray diffraction can measure the strain of the lattice of the semiconductor comprising the bulk of the wafer (see, for example, “High Resolution X-ray Diffractometerty and Topography” D. K. Bowen, B. K. Tanner (1998), CRC Press ISBN 0-8506-6758-5), Chapter 1, pp. 1-13, which is incorporated herein by reference. Since the elastic properties of common semiconductor materials are well known, a measurement of strain can be used to compute stress. Since the measurement of lattice constants depends only on the knowledge of the wavelength of the X-rays and of the angles of incidence and reflection of the X-rays, very accurate measurements of strain can be made by X-ray diffraction. But the slowness of the measurement and the complexity of the apparatus make this more suitable for use as a reference technique than as a routine production metrology technique that needs to measure tens or hundreds of wafers per day. Raman spectroscopy can measure semiconductor lattice strain because the shift of the Raman line depends on the strain of the semiconductor (see, e.g., “Raman Microscopy”, G. Turrell and J. Corset (Eds.), pp 27-277 (1996) Academic Press, ISBN 0-12-189690-0). This will work only of the overlying films on the wafer do not interfere with the Raman lines from the underlying material. The apparatus for Raman spectroscopy is complex compared with that for shape measurement, and the sensitivity and signal-to-noise ratio are poor because the Raman lines in semiconductors are so weak relative to the incident laser line. For all of these reasons Raman is not suitable for routine production measurements.
With respect to overlay metrology, extensive prior art can be found describing many different optical, algorithm and mark architectures which are relied on for this purpose. The current state of the art is, for example, the KLA-Tencor Archer 100 overlay metrology tool, which operates on the principle of high resolution bright field imaging of either box-in-box or periodic (AIM) two-layer metrology structures. With a box-in-box structure, the displacement between the centers of symmetry of two or more features, sequentially generated in a number of patterning steps is calculated by image processing of images acquired through a microscope and stored digitally. This technique further described and analyzed by Neal T. Sullivan, “Semiconductor Pattern Overlay”, in Handbook of Critical Dimensions Metrology and Process Control, pp. 160-188, vol. CR52, SPIE Press (1993). Variations on such box-in-box structures are also described in U.S. Pat. Nos. 6,118,185 and 6,130,750, the disclosures of both of which are incorporated herein by reference.
A known alternative to the box-in-box technique is known as scatterometry overlay. In this technique, information is extracted from the intensity of light reflected from a periodic overlay mark. The overlay mark consists of gratings printed over gratings in subsequent patterning steps. In this approach, several overlay cells, with different intentional offsets between the two gratings of each cell, are formed in close proximity. The difference between the intensities of light scattered from these overlay marks allows a model-free determination of the overlay error. Such grating style targets (sometimes referred to as “AIM” marks) can be denser and more robust, than “box” or ring-type marks resulting in the collection of more process information, as well as target structures that can better withstand the rigors of CMP. The use of such marks is described, e.g., by Adel et al in commonly assigned U.S. Pat. Nos. 6,023,338, 6,921,916 and 6,985,618, all three of which are incorporated herein by reference for all purposes.
As the depth of focus and overlay control required for the smallest dimensions printed on the wafer shrink, simply controlling global wafer stress below some threshold is no longer sufficient. In particular, the rapid thermal annealing (sometimes referred to as spike anneal) needed to anneal semiconductor wafers after certain implant process steps has to heat and cool the wafer very rapidly in order to minimize the time spent at high temperatures to limit diffusion of implanted atoms. This fast heating and cooling subjects the wafer to significant stresses as different parts of the wafer heat and cool at different rates. Some of these stresses may remain “frozen in” after the wafer has cooled. Laser spike anneal uses a laser to rapidly heat the wafer in an attempt to achieve very high surface temperatures in a very short time. However, the laser is typically not powerful enough to heat the whole surface simultaneously. Instead, sections or strips are annealed one at a time eventually covering the whole wafer surface. Because only a part of the wafer is at high temperature at any one time, very high stresses can be generated and some of these stresses remain after processing. Non-uniform stresses in a wafer can distort the local shape of the wafer in complex ways. For example, the wafer may bend both in-plane and out of plane as a result of non-uniform stresses.
The manufacture of modern integrated circuit chips requires very many different patterns to be layered one on another. Each new pattern has to be accurately registered with patterns already on the chip. The patterning tool (e.g., a scanner or stepper) that prints the pattern on the wafer contains subsystems that measure the location, height and tilt of the existing pattern. The time available to make these measurements is limited because these measurements have to be done while the previous wafer is being exposed (or otherwise processed). Consequently, the number of measurements that can be made during such time is limited.
If the stress changes between one patterning step and the next, the shape of the wafer in X, Y and Z can change. If the change in stress is uniform then the shape changes can generally be represented accurately enough as linear distortions of the shape. In such a case, the measurements made by the patterning tool are often sufficiently accurate to correct for the distortions. However, if the changes in stress are non-uniform then the shape changes are complex and linear models may not be accurate enough.
Prior art lithography tools may attempt to make the wafer as flat as possible by using a vacuum chuck to suck the wafer down onto a very precisely machined flat surface. Typically, in order to minimize contact between the wafer backside and the chuck surface, the chuck uses a large number of pins to support the wafer. Because of the vacuum, a combination of atmospheric pressure and gravity forces the wafer down onto the pins and also causes some sag of the wafer between the pins, which are, by design, closely spaced to minimize the sag. The stresses in the wafer, the atmospheric pressure and force of gravity on the wafer and forces of the pins on the wafer where the wafer contacts a pin all interact to determine the shape of the wafer.
Wafer defocus of 50 nm may cause overlay shifts of approximately 10 nm. According to the 2005 ITRS roadmap, at the 32-nm node, the overall budget for overlay accuracy on critical layers is expected to be approximately 5.7 nm 3σ. A fraction of this amount (perhaps 50%) can be allocated to overlay caused by defocus. Based on these numbers, no more than about 15 nm of defocus could be tolerated at the 32-nm node. Without dynamic adjustment of focus and/or overlay, the wafer would be required to be flat to within to within ±15 nm within the area of the die in order to keep overlay registration within the required limits. Scanners do adjust the leveling of each individual die before printing, but the leveling only corrects for average slopes in the X and Y directions (e.g., a tilted wafer plane) and not for vertical distortions on scale lengths shorter than a die.
The complex distortions of the shape of the wafer in X, Y and possibly Z on the chuck due to the non-uniform changes in stress are not adequately accounted for by the patterning tool leading to regions of the wafer where yield is low due to poor alignment of one pattern with earlier patterns on chips in that area of the wafer.
It is within this context that embodiments of the present invention arise.